Modern day mobile communication transceivers must operate with high dynamic range and low power consumption in order to optimize portability. Prior art superheterodyne receiver architectures incorporate complex analogue signal processing circuits to perform signal demodulation when operating as a receiver. In an effort to overcome the requirement of complex analogue signal processing circuitry, prior art receivers have been developed utilized bandpass .SIGMA..DELTA. modulators for digitizing the IF (intermediate frequency) signal, followed by digital demodulation, as disclosed in Longo, L. et al, "A 15-Bit 30 kHz Bandpass Sigma-Delta Modulator", IEEE J. Solid-State Circuits Digest, pp. 226-227, 1993. This prior art approach suffers from the disadvantage of high power consumption since the conversion is performed at a multiple of the IF frequency. The major source of power dissipation in a .SIGMA..DELTA. modulator utilized for IF digitizing, is the operational amplifier needed to implement the loop filter in the ADC (analogue-to-digital convertor) and the active circuits utilized in the mixer, which is usually implemented in the form of a Gilbert multiplier.
In U. Roettcher et al, "A Compatible CMOS-JFET, Pulse Density Modulator for Interpolative High Resolution A/D Conversion", IEEE J. Solid-State Circuits, pp. 446, Vol.SC-21, No. 3, June 1986, replacement of the active loop filter with a passive RC loop filter is suggested for baseband operation. However, this approach suffers from a number of disadvantages. Firstly, resistors are not easily integrable into an integrated circuit. Secondly, prior art converters constructed using RC loop filters suffer from timing jitter problems. Thirdly, an extra mixer is required for direct conversion. The first two disadvantages are common to both baseband and direct conversion applications, while the third problem is specific to direct conversion applications.